IC REVERSE ENGINEERING & DATA EXTRACTION
DATE 14-17 February 2023
HOSTED BY TEXPLAINED
LOCATION Arep Center – 1, Traverse des Brucs – 06560 Valbonne – France
LANGUAGE English or French
REMAINING SEATS 10
The primary goal of this training is to provide Forensics Specialists, Security Professionals and Team Leaders the skills, mindset and background information necessary to successfully perform reverse engineering and data extraction of Integrated Circuits (ICs) as well as evaluate the efficiency of the existing counter-measures. It is designed to give to Integrated Circuit professionals a deep understanding of the complete Reverse-Engineering and Attack chain to help them build more secure designs but also to give to newcomers a detailed overview for a fast ramp-up. Students who complete this course will be familiar with all important classes of low-level hardware attacks (shield and hardware counter-measures bypass – ROM and Flash/EEPROM dump – bus passive and active probing – …) through real world examples covering the entire analysis workflow from the lab to the data analysis. The training will describe modern analysis methods involving automation and discuss the efficiency of modern counter-measures in such a context. Our Hands-on training combines theoretical lectures and practical assignments so students are ready to analyze any Integrated Circuit at different level from SEM pictures and layout information to schematics. A full one-day lab session will complete the picture with demonstrations of how we obtain our base material to conduct our Risk Assessments among other services. The complete Reverse-Engineering workflow will be demonstrated, including Reversing the Integrated Circuit construction, finding the different cores and memories, delayering samples to targeted layers and using a SEM for performing high resolution imagery.
4,000 € / person